OVERVIEW
The Advanced Proficiency in Register Transfer Level (RTL) Design for Working Engineers workshop is a 3-day intensive program aimed at developing expert-level skills in RTL design, logic synthesis, and place-and-route techniques—core components in modern digital design and essential for Industry 4.0 and smart factory applications. Participants will gain a deep understanding of how RTL descriptions are transformed into optimized gate-level representations using advanced optimization strategies such as technology mapping to improve circuit performance, reduce area, and manage power consumption.
In addition, the workshop emphasizes the critical role of place-and-route in physically realizing digital systems, focusing on achieving high performance, managing congestion, and meeting timing constraints through effective gate placement and routing strategies. Through hands-on experience with industry tools, participants will master the end-to-end RTL design flow from RTL coding to physical implementation preparing them to contribute directly to high-efficiency smart factory solutions.
By the end of the course, participants will be able to:
- Understand and applying logic synthesis techniques in SMART Factory environment.
- Transform high-level RTL descriptions into optimized gate-level representations
- Understand place-and-route methodologies and IR 4.0 context.
- Map gate-level netlists onto available resources, minimize wirelength, reduce congestion, and meet timing constraints
- Enhance RTL design implementation skills and improve their ability to create efficient and high-performance designs.
Typically spans 3 days (9am to 5pm).
Nonetheless, we can customize both the program’s duration and schedule to cater to unique client requirements (e.g., compact 1-2 days workshops or extended sessions beyond 3 days).
- RTL Design Engineers
- Digital IC Design Engineers
- ASIC/FPGA Engineers
- Physical Design Engineers
- R&D Engineers in Semiconductor or Industry 4.0 applications
PROPOSED OUTLINE/AGENDA
- Icebreaker & Trainer Introduction
- Program Objectives
Introduction to Logic Synthesis and Place-and-Route and relevancy to IR4.0
- Overview of RTL design flow and explore the importance of logic synthesis and place-and-route.
- Understand the key concepts and terminology.
Overview of Logic Synthesis Techniques
- Understand the concept of technology mapping and gate-level optimization.
- Explore timing constraints and optimization strategies.
Introduction to Place-and-Route
- Walk through a physical design flow for an RTL design and understand the importance of place-and-route in IC design.
- Identify key considerations and challenges.
Overview of Place-and-Route Techniques
- Understand the concept of floorplanning, global and detailed placement, clock tree synthesis (CTS), routing algorithms and congestion management.
Overview of Optimization Techniques
- Understand Static Timing analysis (STA) and timing closure.
- Explore power optimization techniques.
Design Verification and Validation
- Provide an overview of design rule checking (DRC), layout versus schematic (LVS) and physical verification.
Workshop and Real-World Applications
- Practical workshop: applying Logic synthesis and Place-and-route to a Simple CPU Design
- Q&A session, discussions, and conclusion of the training program
PROGRAM METHODOLOGY
- Hands-on Activities: Practical exercises to reinforce theoretical concepts.
- Group Discussions: Opportunities for peer-to-peer learning and exchange of ideas.
- Role Plays: Simulations of realistic situations to build practical skills.
- Feedback Sessions: Reviews and reflections to encourage improvement.
- Problem-solving Exercises: Develop critical thinking and decision-making skills.
- Experiential Learning: Learning by doing, promoting active involvement.
- Interactive Lectures: Engaging presentations by experts in the field.
- Case Studies: Real-world scenarios for learners to apply their knowledge.
- Quizzes & Tests: Regular assessments to track learning progress.
CONTACT US
Our Experts Are Here to Help