OVERVIEW
The VLSI Design and Digital IC Design Techniques workshop is an intensive five-day training program aimed at providing you with advanced knowledge and skills in VLSI design and digital IC design. This workshop will cover a wide range of topics, from the fundamentals of CMOS technology and VLSI design methodologies to advanced digital IC design techniques, including timing analysis, power optimization, and design for testability. Through a combination of in-depth lectures and hands-on sessions with industry-standard EDA tools, you will gain the expertise
By the end of the course, participants will be able to:
- Understand the complete VLSI design flow, from concept to physical implementation.
- Explain CMOS technology fundamentals and apply them in schematic and transistor-level design.
- Perform timing analysis and power optimization for digital ICs using industry-standard techniques.
- Apply design for testability (DFT) strategies to improve circuit reliability and manufacturability.
- Utilize EDA tools such as Cadence and Synopsys for logic synthesis, place-and-route, and verification.
- Conduct static timing analysis (STA) and physical verification including DRC and LVS checks.
- Debug and optimize digital designs for performance, power, and area.
- Collaborate effectively in design teams, leveraging group discussions and problem-solving exercises.
- Demonstrate practical skills through hands-on activities and real-world case studies.
Typically spans 5 days (9am to 5pm).
Nonetheless, we can customize both the program’s duration and schedule to cater to unique client requirements (e.g., compact 2-3 days workshops or extended sessions beyond 5 days).
- Graduate Engineers
- Design Engineers
- Verification Engineers
- Application Engineers
- R&D Engineers
PROPOSED OUTLINE/AGENDA
- Icebreaker & Trainer Introduction
- Program Objectives
- Overview of VLSI design flow and methodologies
- CMOS technology fundamentals
- Schematic design and transistor-level implementation
- Hands-on exercises with basic CMOS circuits
- Timing analysis and clocking strategies
- Power analysis and optimization techniques
- Hands-on exercises with timing and power analysis
- Design for testability (DFT) techniques
- Introduction to EDA tools (e.g., Cadence, Synopsys)
- Logic synthesis and place-and-route (P&R) techniques
- Hands-on exercises with logic synthesis tools
- Implementing simple designs and performing P&R
- Timing verification (Static Timing Analysis, STA)
- Physical verification (Design Rule Check, DRC; Layout Versus Schematic, LVS)
- Hands-on exercises with STA and physical verification tools
- Debugging and optimizing designs
PROGRAM METHODOLOGY
- Hands-on Activities: Practical exercises to reinforce theoretical concepts.
- Group Discussions: Opportunities for peer-to-peer learning and exchange of ideas.
- Role Plays: Simulations of realistic situations to build practical skills.
- Feedback Sessions: Reviews and reflections to encourage improvement.
- Problem-solving Exercises: Develop critical thinking and decision-making skills.
- Experiential Learning: Learning by doing, promoting active involvement.
- Interactive Lectures: Engaging presentations by experts in the field.
- Case Studies: Real-world scenarios for learners to apply their knowledge.
- Quizzes & Tests: Regular assessments to track learning progress.
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